1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a chemical mechanical polishing (CMP) method.
2. Description of the Related Art
High performance and highly integrated semiconductor devices such as 256 mega byte and 1 giga byte dynamic random access memories (DRAM) require ultra large scale integration (ULSI). Technologies for forming fine patterns and three-dimensional multi-layer structures are essential to effectively manufacture highly integrated semiconductor devices. Therefore, it is necessary to introduce a new more efficient and precise process to manufacture semiconductor devices. When multi-layered fine wiring is formed by a pattern forming technology, it is essential to planarize an interlayer dielectric (ILD) layer existing under the fine wiring. A partial planarization processing technology is generally used to planarize a layer of a semiconductor device. More recently, a global planarization technology called chemical mechanical polishing (CMP) for planarizing an entire wafer surface has been in use since the mid 1980's. CMP technology improves processing efficiency of semiconductor devices and the quality of the semiconductor devices formed thereby.
CMP technology is applied in semiconductor device manufacturing, i.e., for planarizing an ILD layer, for planarizing metal wiring, and for planarizing a trench structure in an element isolation process. Accordingly, CMP technology improves the depth of focus (DOF) of exposing light in a photolithography process, allows multi-layer wiring to be formed in fine patterns, and improves the step difference between memory cell areas and adjacent peripheral circuit areas in memory devices. Therefore, after CMP technology was introduced to semiconductor device manufacturing, much development was made with respect to element isolation technology to improve the degree of integration, realize fine pattern structure, and to improve global planarization of multi-wiring semiconductor devices. Due to the above-mentioned advantages of CMP technology, research on CMP equipment, articles of consumption for the CMP equipment, and process design using CMP technology, are continuing.
A trench planarization process of an element isolation process is disclosed in U.S. Pat. No. 5,494,857, titled chemical mechanical planarization of shallow trenches in semiconductor substrates, filed on Feb. 27, 1996 and issued to Digital Equipment Corporation (DEC).
FIGS. 1 and 2 are cross-sectional views describing a CMP method according to conventional technology.
Referring to FIG. 1, a polishing stopper 53 such as a silicon nitride (SiN) layer is formed on a semiconductor substrate. A trench is formed by etching a predetermined area of the semiconductor substrate 51 in order to form the isolation layer. Then, an oxide layer 55 which can operate as the isolation layer is deposited on the semiconductor substrate 51 covering the entire surface of the semiconductor substrate 51. The semiconductor substrate 51 is divided into a field area 12, where a field oxide layer is formed in a relatively wide area, and a pattern area 10 in which a separate element such as a memory cell is formed.
With reference to FIG. 2, an isolation layer 55' for separating adjacent active areas is formed on the surface of the semiconductor substrate by global planarization in which the CMP process is performed on the surface of the semiconductor substrate 51 on which the oxide layer 55 is stacked. In the CMP process, the polishing stopper layer 53, which is formed of a SiN layer, prevents the oxide layer 55 from being polished, by which it is possible to achieve global planarization. To planarize the polishing stopper layer made up of a SiN layer or a boron nitride (BN) layer in the CMP process, silica-based slurry is used. In order to planarize the SiN layer or a polysilicon layer in the CMP process, Ceria-based slurry is used.
However, the CMP method has the following problems. First, a dishing phenomenon (D of FIG. 2) occurs in which a recessed isolation layer 55 and not a flat isolation layer is formed in the field area 12. It is considerably difficult to prevent the occurrence of the dishing phenomenon because the dishing phenomenon occurs naturally even though the CMP process uses a slurry having high polishing selectivity.
Second, a thickness variation of the polishing stopper 53 is generated in the pattern area (A of FIG. 2) which is adjacent to the field area 12. The non-uniform thickness of the polishing stopper 53 deteriorates the electrical performance and the reliability of the semiconductor device when the semiconductor device manufacturing processes are completed.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.